module top_die(
    input clk,
    output valid
);

wire mid_signal;

sub_level1 inst_level1(
    .clk(clk),
    .data_out(mid_signal)
);

endmodule

module sub_level1(
    input clk,
    output [7:0] data_out
);

wire [7:0] internal;

sub_level2 inst_level2(
    .clk(clk),
    .data(internal)
);

assign data_out = internal;

endmodule

module sub_level2(
    input clk,
    output [7:0] data
);

assign data = 8'hAB;

endmodule
